The present invention relates generally to computer system performance modeling, and more particularly to providing improved trace data.
Data processing systems which use virtual addressing in multiple virtual address spaces are well known. Many data processing systems include, for example, a central processing unit (CPU) and a main storage. The CPU contains the sequencing and processing facilities for instruction execution, interruption action, timing functions, initial program loading and other machine related functions. The main storage is directly addressable and provides for high-speed processing of data by the CPU. The main storage may be either physically integrated with the CPU or constructed in stand-alone units.
In general, address spaces reside in main storage wherein an address space is a consecutive sequence of integer numbers (or virtual addresses), together with the specific transformation parameters which allow each number to be associated with a byte location in storage. The sequence starts at zero and proceeds left to right.
When a virtual address is used by a CPU to access main storage, it is first converted, by means of dynamic address translation (DAT), to a real address, and then, by means of prefixing, to an absolute address. DAT uses various levels of tables as transformation parameters and translates a virtual address of a computer system to a real address by means of translation tables. The designation (in the past, including origin and length) of a table is found for use by DAT in a control register or as specified by an access register.
Tracing assists in determining whether problems exist in the data processing system by providing an ongoing record in storage of significant events, or benchmarks. An example of a tracing system is the Console Monitoring System (CMS) Adjunct Tracing System (CATS), which consists of a coherent, sequential and generally contiguous set of architected instruction records which are captured while processing instructions through a data processing system.